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Attack Mcu

Principle and development of PIC24 series single chip microc

Principle and development of PIC24 series single chip microcomputer
Two point one
CPU
Module introduction
PIC
Series MCU
CPU
The kernel is different from the general single chip microcomputer in the structure.
Dual bus architecture, the so-called Harvard architecture. This structure has two kinds of bus, program bus and data bus. Therefore, instruction and data
At the same time, it is easy to implement multi-level instruction pipelining technology (fetch and instruction execution in time).
PIC24
CPU
The kernel uses a modified Harvard architecture, which is independent of the data bus and the program bus, so that it can be effectively eliminated.
The bottleneck of data transmission. The improved Harvard structure mainly lies in: the data bus width is
Sixteen
Program bus width
Twenty-four
A;
Program area and data area can also exchange data
(PSV,
Table read / write
Etc..
Instruction code
Twenty-four
Bit as a unit (in this case called instruction word),
And most of the instructions for single instruction word. Program counter (PC) is 23
The least bit, the
0, so you can address the high
Up to X 4M 24
Bit user program storage space. PIC24F
CPU
The kernel has an instruction set with enhanced features, single cycle instructions and pre
The maximum throughput can be provided by the mechanism. In addition to changing the instruction of the program flow (i.e., the transfer instruction), the two word transfer (MOV.D) instruction
And table operation instructions, the rest of the instructions are executed in a single cycle (called the instruction cycle, and denoted as
Tcy). CPU
Kernel energy
Perform a data (or program data) in each instruction cycle
Memory read operation,
First working register (data) read operation,
A data memory write operations and a program
(instruction) memory read operation. So you can support 3
A parameter of an instruction, and
An instruction cycle can be completed by A + B = C
Operation. Module using REPEAT
Instruction support without overhead program loop structure
The.
Instructions can be interrupted when execution is performed.
PIC24
CPU
There are 16
individual
Sixteen
Bit work register: W0 ~ W15. Each working register can be used as a data, an address, or a
Address offset register usage.
Working register W15
Stack pointer register,
Used for interrupt and subroutine calls.
Working register
W14
Can be used as a stack frame pointer, with LNK
And UNLK
Instructions for use.
CPU
Kernel instruction set architecture (Instruction
Set
Architecture, ISA) in PIC18F
Base of instruction set architecture
On the basis of enhanced and maintained a downward compatibility. All PIC18F
Instructions and addressing modes can be directly supported or passed
Simple macros are supported.
Many ISA
The enhancement function is to improve the efficiency of the compiler
Designed.
Addressing mode support
(no
Addressing, relative addressing, immediate addressing, memory addressing, direct and indirect addressing, and
A symbol 10
Bit offset register indirect addressing mode. Because the focus of this book is not
PIC24
Instructions and assembly
Language programming, so the instructions on the chip function and the way to address the detailed information, please refer to the chip data sheet and the "16"
position
MCU
and
DSC
Programmer's reference manual (70157e_cn)".
CPU
The kernel has a high speed of 17
position
X
Seventeen
A bit multiplier, the multiplier is supported by a symbol, unsigned, and mixed mode 16
position
X16
Bit or 8
position
X
Eight
Bit integer multiplication. All multiplication instructions execute only one instruction cycle. Kernel support 32
Bit divided by 16
And
Sixteen
Bit divided by 16
Signed and unsigned division operations of an integer. All division instructions are 19
Instruction cycle,
In the division operation instruction execution time can respond to the interrupt
.
PIC24
Has a perfect function of the interrupt system, support up to 8
Non mask interrupt and
Fifty-four
One (PIC24FJ64GAxxx
by
Forty
) a mask can be interrupted. Shielding interrupt
Seven
Priority, the user can be programmed to set the priority of each interrupt source. PIC24
in
Interrupt system support interrupt nesting, and can be programmed to allow for interrupt nesting.
and
PIC
The
Eight
Different bit machine, PIC24
Series no longer have a headache program memory and data memory paging
The operation is completely linear, and the stack is in the data storage, and the depth of the stack is not limited. No doubt, all of these are for use.
User programming brings a lot of convenience.
PIC24
Support program memory space
RAM
Visual manipulation (Space Visibility Program, PSV)
, using the program
Memory space visibility page register (PSVPAG) data memory can be high
32K
Bytes mapped to any 16K
word
(32K
Program space for a unit. The mapping function of the data space to the program space allows any instruction to access the data space.
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